itemprop="text">
Reading through some great
presentations on low latency computing. They had a reference to IBM's XL C/C++ compiler
data cache operation href="http://publib.boulder.ibm.com/infocenter/cellcomp/v101v121/index.jsp?topic=/com.ibm.xlcpp101.cell.doc/compiler_ref/bif_dcbt.html"
rel="noreferrer">__dcbt (Data Cache Block Touch) for their href="http://en.wikipedia.org/wiki/Cell_(microprocessor)"
rel="noreferrer">cell compiler. The operation loads a block of memory into
L1 cache.
Does Visual Studio (or G++ or Intel)
have similar functionality for Intel Processors? If so and the solution is platform
specific (i.e. Windows or *nix only) please say so.
Yes, Visual Studio supports all the SSE and
MMX intrinsic operations. The cache control operations are briefly described here: href="http://www.tommesani.com/SSECacheabilityControl.html" rel="nofollow
noreferrer">http://www.tommesani.com/SSECacheabilityControl.html
and
explained at length in rel="nofollow noreferrer">Intel's instruction set
reference.
Microsoft href="http://msdn.microsoft.com/en-us/library/cyxt4d09(VS.71).aspx" rel="nofollow
noreferrer">documents their intrinsics for cache control at MSDN. Although
they look like functions, the compiler actually boils them down to the appropriate
hardware instruction. Be sure to look at both their SSE1 and SSE2 cache control
instructions, which they list under separate categories (see the expanding tree on the
left side of their page).
The x86 equivalent to
dcbt is _mm_prefetch. There is no
direct equivalent to dcbz, but the closest analogue is
_mm_stream_si128.
I
believe GCC uses the same intrinsic names (as they are taken from the Intel
compiler).
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