php - file_get_contents shows unexpected output while reading a file

I want to output an inline jpg image as a base64 encoded string, however when I do this :

$contents = file_get_contents($filename);
print "";

Where $filename is a local text file with the base64 image. The output is as follows :

And obiously the image is not rendered, but where does  come from ? It is not in the text file. If removed, the image is displayed properly.

Answer

It's a Unicode Byte-Order Mark. The file was saved with an editor that added the BOM to indicate the file is encoded as UTF-8. So those bytes actually are in the file, but a text editor just won't show it since it's not text. For storing this kind of data you'll want to remove the BOM. Easiest way would be to configure your editor not to add the BOM, but if you don't have influence over the creation process of the file you could to it on-the-fly in your script too:

print "";

java.util.scanner - Last line of input not scanning in Java Scanner Class

I am trying to work on some stuff using the Scanner for input, but for some reason, the scanner is failing me.

I have the following code running, nothing complex:

while(scan.hasNextLine())
    {
        System.out.println(scan.nextLine());
    }

Just as a test bed to make sure everything is being input correctly. If I copy my test material, say

5

4
3
2
1

The output omits the last line. I am pretty sure that it is because nextLine will only return a string if there is a string after it, even if it is empty, but I need it to work this way for the way I will eventually input the data to work. Does anyone know how I can fix this? My only guesses were to either use something other that scanner or to somehow append an empty string to the end of the input, but I wasn't sure how to do the second one, and I didn't think a different scanner-like thing would work. Thanks in advance!

Answer

Your last line MIGHT not have a "enter" char. So it does not treat it as the end of line. Try

> 5
> 4
> 3
> 2
> 1
> 

How to implement Random.nextDouble() in javascript?

I am using Math.floor((Math.random() * max-min)+min) for random number generation,
what is the difference between this function and random.nextDouble() ?
How to implement random.nextDouble in Javascript?

What's the strangest corner case you've seen in C# or .NET?

I collect a few corner cases and brain teasers and would always like to hear more. The page only really covers C# language bits and bobs, but I also find core .NET things interesting too. For example, here's one which isn't on the page, but which I find incredible:

string x = new string(new char[0]);
string y = new string(new char[0]);
Console.WriteLine(object.ReferenceEquals(x, y));

I'd expect that to print False - after all, "new" (with a reference type) always creates a new object, doesn't it? The specs for both C# and the CLI indicate that it should. Well, not in this particular case. It prints True, and has done on every version of the framework I've tested it with. (I haven't tried it on Mono, admittedly...)

Just to be clear, this is only an example of the kind of thing I'm looking for - I wasn't particularly looking for discussion/explanation of this oddity. (It's not the same as normal string interning; in particular, string interning doesn't normally happen when a constructor is called.) I was really asking for similar odd behaviour.

Any other gems lurking out there?

Answer

I think I showed you this one before, but I like the fun here - this took some debugging to track down! (the original code was obviously more complex and subtle...)

    static void Foo() where T : new()
    {
        T t = new T();
        Console.WriteLine(t.ToString()); // works fine
        Console.WriteLine(t.GetHashCode()); // works fine
        Console.WriteLine(t.Equals(t)); // works fine

        // so it looks like an object and smells like an object...

        // but this throws a NullReferenceException...

        Console.WriteLine(t.GetType());
    }

So what was T...

Answer: any Nullable - such as int?. All the methods are overridden, except GetType() which can't be; so it is cast (boxed) to object (and hence to null) to call object.GetType()... which calls on null ;-p

---

Update: the plot thickens... Ayende Rahien threw down a similar challenge on his blog, but with a where T : class, new():

private static void Main() {
    CanThisHappen();
}

public static void CanThisHappen() where T : class, new() {
    var instance = new T(); // new() on a ref-type; should be non-null, then
    Debug.Assert(instance != null, "How did we break the CLR?");
}

But it can be defeated! Using the same indirection used by things like remoting; warning - the following is pure evil:

class MyFunnyProxyAttribute : ProxyAttribute {
    public override MarshalByRefObject CreateInstance(Type serverType) {
        return null;
    }
}
[MyFunnyProxy]

class MyFunnyType : ContextBoundObject { }

With this in place, the new() call is redirected to the proxy (MyFunnyProxyAttribute), which returns null. Now go and wash your eyes!

android - How to resolve Attempt to invoke virtual method 'boolean java.lang.String.equalsIgnoreCase(java.lang.String)?

I have an app in which i am getting error "Attempt to invoke virtual method 'boolean java.lang.String.equalsIgnoreCase(java.lang.String)" please explain meaning and solution for that

code:-

 String receivedResult = parseJsonResultSetFav(result);
            if (receivedResult.equalsIgnoreCase("SUCCESS")) {
                CustomerTicketDialogClass ctdc = new CustomerTicketDialogClass(getActivity(),
                        "successful", "successfully sent mail to your email id ", "ViewDetails");
                ctdc.show();

                ctdc.setCanceledOnTouchOutside(false);
            } else {
                CustomerTicketDialogClass ctdc = new CustomerTicketDialogClass(getActivity(),
                        "failure", receivedResult, "ViewDetails");
                ctdc.show();
                ctdc.setCanceledOnTouchOutside(false);
            }

unicode - What characters can be used for up/down triangle (arrow without stem) for display in HTML?

I'm looking for a HTML or ASCII character which is a triangle pointing up or down so that I can use it as a toggle switch.

I found ↑ (↑), and ↓ (↓) - but those have a narrow stem. I'm looking just for the HTML arrow "head".

Answer

Unicode arrows heads:

• ▲ - U+25B2 BLACK UP-POINTING TRIANGLE



• ▼ - U+25BC BLACK DOWN-POINTING TRIANGLE


• ▴ - U+25B4 SMALL BLACK UP-POINTING TRIANGLE


• ▾ - U+25BE SMALL BLACK DOWN-POINTING TRIANGLE

For ▲ and ▼ use ▲ and ▼ respectively if you cannot include Unicode characters directly (use UTF-8!).

Note that the font support for the smaller versions is not as good. Better to use the large versions in smaller font.

More Unicode arrows are at:

Lastly, these arrows are not ASCII, including ↑ and ↓: they are Unicode.

javascript - Check if a variable is of function type

Suppose I have any variable, which is defined as follows:

var a = function() {/* Statements */};

I want a function which checks if the type of the variable is function-like. i.e. :

function foo(v) {if (v is function type?) {/* do something */}};
foo(a);

How can I check if the variable a is of type Function in the way defined above?

Answer

Sure underscore's way is more efficient, but the best way to check, when efficiency isn't an issue, is written on underscore's page linked by @Paul Rosania.

Inspired by underscore, the final isFunction function is as follows:

function isFunction(functionToCheck) {
 return functionToCheck && {}.toString.call(functionToCheck) === '[object Function]';
}

C++: Why is 'operator+=' defined but not 'operator+' for strings?

How come operator+= is defined for std::string but operator+ is not defined? See my MWE below (http://ideone.com/OWQsJk).

#include 

#include 
using namespace std;

int main() {  
    string first;
    first = "Day";
    first += "number";
    cout << "\nfirst = " << first << endl;

    string second;

    //second = "abc" + "def";       // This won't compile
    cout << "\nsecond = " << second << endl;
    return 0;
}

Answer

You need to convert one of the raw string literals to std::string explicitly. You can do it like others already mentioned:

second = std::string("abc") + "def";

or with C++14, you will be able to use

using namespace std::literals;
second = "abc"s + "def";
// note       ^

Undo working copy modifications of one file in Git?

After the last commit, I modified a bunch of files in my working copy, but I want to undo the changes to one of those files, as in reset it to the same state as the most recent commit.

However, I only want to undo the working copy changes of just that one file alone, nothing else with it.

How do I do that?

Answer

You can use

git checkout -- file

You can do it without the -- (as suggested by nimrodm), but if the filename looks like a branch or tag (or other revision identifier), it may get confused, so using -- is best.

You can also check out a particular version of a file:

git checkout v1.2.3 -- file         # tag v1.2.3
git checkout stable -- file         # stable branch
git checkout origin/master -- file  # upstream master
git checkout HEAD -- file           # the version from the most recent commit
git checkout HEAD^ -- file          # the version before the most recent commit

string - Detecting Vowels vs Consonants In Python

Change:

if first == "a" or "e" or "i" or "o" or "u":

to:

if first in ('a', 'e', 'i', 'o', 'u'):  #or `if first in 'aeiou'`

first == "a" or "e" or "i" or "o" or "u" is always True because it is evaluated as

(first == "a") or ("e") or ("i") or ("o") or ("u"), as an non-empty string is always True so this gets evaluated to True.

>>> bool('e')
True

javascript - $(document).ready equivalent without jQuery

I have a script that uses $(document).ready, but it doesn't use anything else from jQuery. I'd like to lighten it up by removing the jQuery dependency.

How can I implement my own $(document).ready functionality without using jQuery? I know that using window.onload will not be the same, as window.onload fires after all images, frames, etc. have been loaded.

java - Updated global variables does not reflect inside ValueEventListener's onCancelled method

I am currently testing a ValueEventListener's onCancelled() method to implement proper firebase error management. I have succeeded thus far, onCancelled() was firing well. I have set-up the firebase rules for a specific node to return a permission denied error.

But I'm confused as to how global variables are managed inside the onCancelled() method. Why does it seem like global variables retain their default initial state when called inside onCancelled()? Updates on the variables from outside do not reflect when they're called inside this method but are reflected when called from onDataChange() and other in-Activity methods.

UPDATE NO. 2:
Inserted the firebase auth codes, added test flow execution. Also added the log outputs as suggested by @Doug Stevenson. From the logs, it seems onCancelled() was only called once (during app onCreate()). I think that's what gave me the wrong impression that currentSynId was never changed coz its value is still Hello!!! there, and I didn't look at the after-logs before.

But now I see there's a log W/RepoOperation: updateChildren at /2014 failed: DatabaseError: Permission denied that fires everytime R.id.btn_sync is called (and never again the log for onCancelled where the updated currentSyncId should be). Maybe I should rephrase my question? I would like to catch the instance where/when the current cancellations logs are fired. Thanks.

UPDATE NO. 1 I took out relevant pieces from the complete codes and replaced the previous snippets:

...


public class Demo extends AppCompatActivity {

    // Database reference
    private DatabaseReference mFirebaseMain2014;

    //
    private FirebaseAuth mAuth;

    public String currentSyncId = "Hello!!!";


    @Override
    protected void onCreate(Bundle savedInstanceState) {
        super.onCreate(savedInstanceState);
        setContentView(R.layout.activity_demo);

        // Initialize firebase auth
        mAuth = FirebaseAuth.getInstance();
        mAuth.addAuthStateListener(new FirebaseAuth.AuthStateListener() {
            @Override
            public void onAuthStateChanged(@NonNull FirebaseAuth firebaseAuth) {

                if(mAuth.getCurrentUser() != null) {
                    Log.d("MAIN", "A user was logged in: " + mAuth.getCurrentUser().getUid());
                    initDatabase(mAuth.getCurrentUser().getUid());
                }


                findViewById(R.id.btn_sync).setOnClickListener(new View.OnClickListener() {
                    @Override
                    public void onClick(View v) {
                        syncData();

                    }
                });

                findViewById(R.id.btn_echovalue).setOnClickListener(new View.OnClickListener() {
                    @Override
                    public void onClick(View v) {
                        printId();
                    }
                });
            }

        });
    }


    /**
     * Initialize database and listeners
     * @param userid
     */
    public void initDatabase(String userid){
        Log.d("MAIN", "Initialized databases");

        // Initialize database references
        mFirebaseMain2014 = FirebaseDatabase.getInstance().getReference("2014");
        mFirebaseMain2014.child("app_final/" + userid).addValueEventListener(new ValueEventListener() {
            @Override
            public void onDataChange(@NonNull DataSnapshot dataSnapshot) {
                // data processing here..
            }

            @Override
            public void onCancelled(@NonNull DatabaseError databaseError) {

                Log.d("MAIN-ON-CANCELLED-EVENT", "An error occurred while syncing data: " +
                        databaseError.getMessage() + "\n id: " + currentSyncId);
            }
        });
    }


    /**
     * Initiate firebase syncing (which will lead to Permission-Denied
     */

    public void syncData(){
        // Log values
        Log.d("MAIN", "Initiating sync...");
        currentSyncId = "00001";

        // Set the dummy data that will be sent to firebase
        HashMap map = new HashMap();
        map.put(currentSyncId, "Hello, world!");

        // Sync dummy data to firebase

        mFirebaseMain2014.updateChildren(map);

        Log.d("MAIN", "Sync called.");
    }


    /**
     * Print the contents of global currentSyncId
     */
    public void printId(){

        Log.d("MAIN", "PRINTING CURRENT id value: " + currentSyncId + ", userid: " + getAuthUserId());
    }


    public String getAuthUserId(){
        return mAuth.getCurrentUser().getUid();
    }
}

TEST FLOW

1. Loaded the app


2. Pressed the R.id.btn_echovalue button


3. Pressed the R.id.btn_sync button


4. Pressed the R.id.btn_echovalue button

LOG OUTPUT

D/FirebaseAuth: Notifying id token listeners about user ( WN1b3pJyggNOvaoHDdtPsHrFLmG3 ).
I/FirebaseInitProvider: FirebaseApp initialization successful
D/FirebaseApp: Notifying auth state listeners.
               Notified 0 auth state listeners.
D/MAIN: A user was logged in: WN1b3pJyggNOvaoHDdtPsHrFLmG3
D/MAIN: Initialized databases
W/SyncTree: Listen at /2014/app_final/WN1b3pJyggNOvaoHDdtPsHrFLmG3 failed: DatabaseError: Permission denied
D/MAIN-ON-CANCELLED-EVENT: An error occurred while syncing data: Permission denied

                            id: Hello!!!
I/FirebaseAuth: [FirebaseAuth:] Loading module via FirebaseOptions.
                [FirebaseAuth:] Preparing to create service connection to gms implementation
D/FirebaseAuth: Notifying id token listeners about user ( WN1b3pJyggNOvaoHDdtPsHrFLmG3 ).
D/FirebaseApp: Notifying auth state listeners.
               Notified 1 auth state listeners.
D/MAIN: PRINTING CURRENT id value: Hello!!!, userid: WN1b3pJyggNOvaoHDdtPsHrFLmG3
D/MAIN: Initiating sync...
D/MAIN: Sync called.
W/RepoOperation: updateChildren at /2014 failed: DatabaseError: Permission denied

D/MAIN: PRINTING CURRENT id value: 00001, userid: WN1b3pJyggNOvaoHDdtPsHrFLmG3

The Log inside onCancelled() was firing well. I expect to see

MAIN: An error occurred while syncing data: Permission denied.
Sync ID: 0001

But instead, I see:

MAIN: An error occurred while syncing data: Permission denied.
Sync ID: Hello!!!

I need to keep track of the currentSyncId when the onCancelled() was fired so I can reset its local sync status references in the app to false.

I have looked for similar cases and questions but the closest threads I found are how to call onCancelled here and here, and a few references to onDataChange. I found an interesting answer by @vincrichaud here, but I'm not really sure if this is applicable to firebase android as well.

TIA!

JavaScript chop/slice/trim off last character in string

I have a string, 12345.00, and I would like it to return 12345.0.

I have looked at trim, but it looks like it is only trimming whitespace and slice which I don't see how this would work. Any suggestions?

Answer

You can use the substring function:

let str = "12345.00";
str = str.substring(0, str.length - 1);
console.log(str);

This is the accepted answer, but as per the conversations below, the slice syntax is much clearer:

let str = "12345.00";
str = str.slice(0, -1); 
console.log(str);

r - How to edit a .yml file in Shiny

I have a Shiny application which pulls data from various APIs and databases. All the sensitive data pertaining to credentials, usernames, passwords etc. are stored in a config.yml file. The code within the Shiny app calls variables within the config.yml file for connecting to different APIs/databases.

I have also created an administrator login for the Shiny application and want to provide access to the administrator for making changes in the config.yml file. The Shiny app has a separate tab called Admin whiich opens up when the administrator logs in. How can I open the config.yml file and allow edits by the administrator and save it?

Answer

I created a tab for the configuration file and using Shiny Ace as editor:

library(shinyAce) 

# UI

aceEditor(
          outputId = "someID",

          value = read.delim("config.yml"),
          placeholder = "Connection configuration file"
         ), 

        actionButton("save", label = "Save Configuration")

# Sever

 observeEvent(input$save, {
    write(x = input$someID, file = "config.yml")

    print("file saved")

    })

Then you can call to the config.yml and apply the configurations.

c++ - In C, importance and usage of extern storage class specifier

Actually I want to know the importance of extern.

First I wrote some code :

file1.h

extern int i;

file2.c

#include
#include "file1.h"
 int i=20;
int main()
{
   printf("%d",i);
   return 0;
}

Now my question is that: what is the use of extern variable when I have to define the i in file2.c, declaring in file1.h is in which way useful to me .

sudhanshu

assembly - Micro fusion and addressing modes

I have found something unexpected (to me) using the Intel® Architecture Code Analyzer (IACA).

The following instruction using [base+index] addressing

addps xmm1, xmmword ptr [rsi+rax*1]

does not micro-fuse according to IACA. However, if I use [base+offset] like this

addps xmm1, xmmword ptr [rsi]

IACA reports that it does fuse.

Section 2-11 of the Intel optimization reference manual gives the following as an example "of micro-fused micro-ops that can be handled by all decoders"

FADD DOUBLE PTR [RDI + RSI*8]

and Agner Fog's optimization assembly manual also gives examples of micro-op fusion using [base+index] addressing. See, for example, Section 12.2 "Same example on Core2". So what's the correct answer?

Answer

In the decoders and uop-cache, addressing mode doesn't affect micro-fusion (except that an instruction with an immediate operand can't micro-fuse a RIP-relative addressing mode).

But some combinations of uop and addressing mode can't stay micro-fused in the ROB (in the out-of-order core), so Intel SnB-family CPUs "un-laminate" when necessary, at some point before the issue/rename stage. For issue-throughput, and out-of-order window size (ROB-size), fused-domain uop count after un-lamination is what matters.

Intel's optimization manual describes un-lamination for Sandybridge in Section 2.3.2.4: Micro-op Queue and the Loop Stream Detector (LSD), but doesn't describe the changes for any later microarchitectures.

UPDATE: Now Intel manual has a detailed section to describe un-lamination for Haswell. See section 2.3.5 Unlamination. And a brief description for SandyBridge is in section 2.4.2.4.

---

The rules, as best I can tell from experiments on SnB, HSW, and SKL:

• SnB (and I assume also IvB): indexed addressing modes are always un-laminated, others stay micro-fused. IACA is (mostly?) correct.


• HSW, SKL: These only keep an indexed ALU instruction micro-fused if it has 2 operands and treats the dst register as read-modify-write. Here "operands" includes flags, meaning that adc and cmov don't micro-fuse. Most VEX-encoded instructions also don't fuse since they generally have three operands (so paddb xmm0, [rdi+rbx] fuses but vpaddb xmm0, xmm0, [rdi+rbx] doesn't). Finally, the occasional 2-operand instruction where the first operand is write only, such as pabsb xmm0, [rax + rbx] also do not fuse. IACA is wrong, applying the SnB rules.

Related: simple (non-indexed) addressing modes are the only ones that the dedicated store-address unit on port7 (Haswell and later) can handle, so it's still potentially useful to avoid indexed addressing modes for stores. (A good trick for this is to address your dst with a single register, but src with dst+(initial_src-initial_dst). Then you only have to increment the dst register inside a loop.)

Note that some instructions never micro-fuse at all (even in the decoders/uop-cache). e.g. shufps xmm, [mem], imm8, or vinsertf128 ymm, ymm, [mem], imm8, are always 2 uops on SnB through Skylake, even though their register-source versions are only 1 uop. This is typical for instructions with an imm8 control operand plus the usual dest/src1, src2 register/memory operands, but there are a few other cases. e.g. PSRLW/D/Q xmm,[mem] (vector shift count from a memory operand) doesn't micro-fuse, and neither does PMULLD.

See also this post on Agner Fog's blog for discussion about issue throughput limits on HSW/SKL when you read lots of registers: Lots of micro-fusion with indexed addressing modes can lead to slowdowns vs. the same instructions with fewer register operands: one-register addressing modes and immediates. We don't know the cause yet, but I suspect some kind of register-read limit, maybe related to reading lots of cold registers from the PRF.

---

Test cases, numbers from real measurements: These all micro-fuse in the decoders, AFAIK, even if they're later un-laminated.

# store
mov        [rax], edi  SnB/HSW/SKL: 1 fused-domain, 2 unfused.  The store-address uop can run on port7.
mov    [rax+rsi], edi  SnB: unlaminated.  HSW/SKL: stays micro-fused.  (The store-address can't use port7, though).
mov [buf +rax*4], edi  SnB: unlaminated.  HSW/SKL: stays micro-fused.

# normal ALU stuff
add    edx, [rsp+rsi]  SnB: unlaminated.  HSW/SKL: stays micro-fused.  
# I assume the majority of traditional/normal ALU insns are like add

Three-input instructions that HSW/SKL may have to un-laminate

vfmadd213ps xmm0,xmm0,[rel buf] HSW/SKL: stays micro-fused: 1 fused, 2 unfused.
vfmadd213ps xmm0,xmm0,[rdi]     HSW/SKL: stays micro-fused
vfmadd213ps xmm0,xmm0,[0+rdi*4] HSW/SKL: un-laminated: 2 uops in fused & unfused-domains.
     (So indexed addressing mode is still the condition for HSW/SKL, same as documented by Intel for SnB)

# no idea why this one-source BMI2 instruction is unlaminated
# It's different from ADD in that its destination is write-only (and it uses a VEX encoding)
blsi   edi, [rdi]       HSW/SKL: 1 fused-domain, 2 unfused.

blsi   edi, [rdi+rsi]   HSW/SKL: 2 fused & unfused-domain.


adc         eax, [rdi] same as cmov r, [rdi]
cmove       ebx, [rdi]   Stays micro-fused.  (SnB?)/HSW: 2 fused-domain, 3 unfused domain.  
                         SKL: 1 fused-domain, 2 unfused.

# I haven't confirmed that this micro-fuses in the decoders, but I'm assuming it does since a one-register addressing mode does.

adc   eax, [rdi+rsi] same as cmov r, [rdi+rsi]

cmove ebx, [rdi+rax]  SnB: untested, probably 3 fused&unfused-domain.
                      HSW: un-laminated to 3 fused&unfused-domain.  
                      SKL: un-laminated to 2 fused&unfused-domain.

I assume that Broadwell behaves like Skylake for adc/cmov.

It's strange that HSW un-laminates memory-source ADC and CMOV. Maybe Intel didn't get around to changing that from SnB before they hit the deadline for shipping Haswell.

Agner's insn table says cmovcc r,m and adc r,m don't micro-fuse at all on HSW/SKL, but that doesn't match my experiments. The cycle counts I'm measuring match up with the the fused-domain uop issue count, for a 4 uops / clock issue bottleneck. Hopefully he'll double-check that and correct the tables.

Memory-dest integer ALU:

add        [rdi], eax  SnB: untested (Agner says 2 fused-domain, 4 unfused-domain (load + ALU  + store-address + store-data)
                       HSW/SKL: 2 fused-domain, 4 unfused.
add    [rdi+rsi], eax  SnB: untested, probably 4 fused & unfused-domain
                       HSW/SKL: 3 fused-domain, 4 unfused.  (I don't know which uop stays fused).
                  HSW: About 0.95 cycles extra store-forwarding latency vs. [rdi] for the same address used repeatedly.  (6.98c per iter, up from 6.04c for [rdi])
                  SKL: 0.02c extra latency (5.45c per iter, up from 5.43c for [rdi]), again in a tiny loop with dec ecx/jnz



adc     [rdi], eax      SnB: untested
                        HSW: 4 fused-domain, 6 unfused-domain.  (same-address throughput 7.23c with dec, 7.19c with sub ecx,1)
                        SKL: 4 fused-domain, 6 unfused-domain.  (same-address throughput ~5.25c with dec, 5.28c with sub)
adc     [rdi+rsi], eax  SnB: untested
                        HSW: 5 fused-domain, 6 unfused-domain.  (same-address throughput = 7.03c)
                        SKL: 5 fused-domain, 6 unfused-domain.  (same-address throughput = ~5.4c with sub ecx,1 for the loop branch, or 5.23c with dec ecx for the loop branch.)

Yes, that's right, adc [rdi],eax / dec ecx / jnz runs faster than the same loop with add instead of adc on SKL. I didn't try using different addresses, since clearly SKL doesn't like repeated rewrites of the same address (store-forwarding latency higher than expected. See also this post about repeated store/reload to the same address being slower than expected on SKL.

Memory-destination adc is so many uops because Intel P6-family (and apparently SnB-family) can't keep the same TLB entries for all the uops of a multi-uop instruction, so it needs an extra uop to work around the problem-case where the load and add complete, and then the store faults, but the insn can't just be restarted because CF has already been updated. Interesting series of comments from Andy Glew (@krazyglew).

Presumably fusion in the decoders and un-lamination later saves us from needing microcode ROM to produce more than 4 fused-domain uops from a single instruction for adc [base+idx], reg.

---

Why SnB-family un-laminates:

Sandybridge simplified the internal uop format to save power and transistors (along with making the major change to using a physical register file, instead of keeping input / output data in the ROB). SnB-family CPUs only allow a limited number of input registers for a fused-domain uop in the out-of-order core. For SnB/IvB, that limit is 2 inputs (including flags). For HSW and later, the limit is 3 inputs for a uop. I'm not sure if memory-destination add and adc are taking full advantage of that, or if Intel had to get Haswell out the door with some instructions

Nehalem and earlier have a limit of 2 inputs for an unfused-domain uop, but the ROB can apparently track micro-fused uops with 3 input registers (the non-memory register operand, base, and index).

---

So indexed stores and ALU+load instructions can still decode efficiently (not having to be the first uop in a group), and don't take extra space in the uop cache, but otherwise the advantages of micro-fusion are essentially gone for tuning tight loops. "un-lamination" happens before the 4-fused-domain-uops-per-cycle issue/retire width out-of-order core. The fused-domain performance counters (uops_issued / uops_retired.retire_slots) count fused-domain uops after un-lamination.

Intel's description of the renamer (Section 2.3.3.1: Renamer) implies that it's the issue/rename stage which actually does the un-lamination, so uops destined for un-lamination may still be micro-fused in the 28/56/64 fused-domain uop issue queue / loop-buffer (aka the IDQ).

TODO: test this. Make a loop that should just barely fit in the loop buffer. Change something so one of the uops will be un-laminated before issuing, and see if it still runs from the loop buffer (LSD), or if all the uops are now re-fetched from the uop cache (DSB). There are perf counters to track where uops come from, so this should be easy.

Harder TODO: if un-lamination happens between reading from the uop cache and adding to the IDQ, test whether it can ever reduce uop-cache bandwidth. Or if un-lamination happens right at the issue stage, can it hurt issue throughput? (i.e. how does it handle the leftover uops after issuing the first 4.)

---

(See the a previous version of this answer for some guesses based on tuning some LUT code, with some notes on vpgatherdd being about 1.7x more cycles than a pinsrw loop.)

Experimental testing on SnB

The HSW/SKL numbers were measured on an i5-4210U and an i7-6700k. Both had HT enabled (but the system idle so the thread had the whole core to itself). I ran the same static binaries on both systems, Linux 4.10 on SKL and Linux 4.8 on HSW, using ocperf.py. (The HSW laptop NFS-mounted my SKL desktop's /home.)

The SnB numbers were measured as described below, on an i5-2500k which is no longer working.

Confirmed by testing with performance counters for uops and cycles.

I found a table of PMU events for Intel Sandybridge, for use with Linux's perf command. (Standard perf unfortunately doesn't have symbolic names for most hardware-specific PMU events, like uops.) I made use of it for a recent answer.

ocperf.py provides symbolic names for these uarch-specific PMU events, so you don't have to look up tables. Also, the same symbolic name works across multiple uarches. I wasn't aware of it when I first wrote this answer.

To test for uop micro-fusion, I constructed a test program that is bottlenecked on the 4-uops-per-cycle fused-domain limit of Intel CPUs. To avoid any execution-port contention, many of these uops are nops, which still sit in the uop cache and go through the pipeline the same as any other uop, except they don't get dispatched to an execution port. (An xor x, same, or an eliminated move, would be the same.)

Test program: yasm -f elf64 uop-test.s && ld uop-test.o -o uop-test

GLOBAL _start
_start:
    xor eax, eax
    xor ebx, ebx
    xor edx, edx
    xor edi, edi
    lea rsi, [rel mydata]   ; load pointer

    mov ecx, 10000000
    cmp dword [rsp], 2      ; argc >= 2
    jge .loop_2reg

ALIGN 32
.loop_1reg:
    or eax, [rsi + 0]
    or ebx, [rsi + 4]
    dec ecx
    nop

    nop
    nop
    nop
    jg .loop_1reg
;   xchg r8, r9     ; no effect on flags; decided to use NOPs instead

    jmp .out

ALIGN 32
.loop_2reg:

    or eax, [rsi + 0 + rdi]
    or ebx, [rsi + 4 + rdi]
    dec ecx
    nop
    nop
    nop
    nop
    jg .loop_2reg

.out:

    xor edi, edi
    mov eax, 231    ;  exit(0)
    syscall

SECTION .rodata
mydata:
db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff

I also found that the uop bandwidth out of the loop buffer isn't a constant 4 per cycle, if the loop isn't a multiple of 4 uops. (i.e. it's abc, abc, ...; not abca, bcab, ...). Agner Fog's microarch doc unfortunately wasn't clear on this limitation of the loop buffer. See Is performance reduced when executing loops whose uop count is not a multiple of processor width? for more investigation on HSW/SKL. SnB may be worse than HSW in this case, but I'm not sure and don't still have working SnB hardware.

I wanted to keep macro-fusion (compare-and-branch) out of the picture, so I used nops between the dec and the branch. I used 4 nops, so with micro-fusion, the loop would be 8 uops, and fill the pipeline with at 2 cycles per 1 iteration.

In the other version of the loop, using 2-operand addressing modes that don't micro-fuse, the loop will be 10 fused-domain uops, and run in 3 cycles.

Results from my 3.3GHz Intel Sandybridge (i5 2500k). I didn't do anything to get the cpufreq governor to ramp up clock speed before testing, because cycles are cycles when you aren't interacting with memory. I've added annotations for the performance counter events that I had to enter in hex.

testing the 1-reg addressing mode: no cmdline arg

$ perf stat -e task-clock,cycles,instructions,r1b1,r10e,r2c2,r1c2,stalled-cycles-frontend,stalled-cycles-backend ./uop-test


Performance counter stats for './uop-test':

     11.489620      task-clock (msec)         #    0.961 CPUs utilized
    20,288,530      cycles                    #    1.766 GHz
    80,082,993      instructions              #    3.95  insns per cycle
                                              #    0.00  stalled cycles per insn
    60,190,182      r1b1  ; UOPS_DISPATCHED: (unfused-domain.  1->umask 02 -> uops sent to execution ports from this thread)
    80,203,853      r10e  ; UOPS_ISSUED: fused-domain
    80,118,315      r2c2  ; UOPS_RETIRED: retirement slots used (fused-domain)

   100,136,097      r1c2  ; UOPS_RETIRED: ALL (unfused-domain)
       220,440      stalled-cycles-frontend   #    1.09% frontend cycles idle
       193,887      stalled-cycles-backend    #    0.96% backend  cycles idle

   0.011949917 seconds time elapsed

testing the 2-reg addressing mode: with a cmdline arg

$ perf stat -e task-clock,cycles,instructions,r1b1,r10e,r2c2,r1c2,stalled-cycles-frontend,stalled-cycles-backend ./uop-test x


 Performance counter stats for './uop-test x':

         18.756134      task-clock (msec)         #    0.981 CPUs utilized
        30,377,306      cycles                    #    1.620 GHz
        80,105,553      instructions              #    2.64  insns per cycle
                                                  #    0.01  stalled cycles per insn
        60,218,693      r1b1  ; UOPS_DISPATCHED: (unfused-domain.  1->umask 02 -> uops sent to execution ports from this thread)
       100,224,654      r10e  ; UOPS_ISSUED: fused-domain
       100,148,591      r2c2  ; UOPS_RETIRED: retirement slots used (fused-domain)

       100,172,151      r1c2  ; UOPS_RETIRED: ALL (unfused-domain)
           307,712      stalled-cycles-frontend   #    1.01% frontend cycles idle
         1,100,168      stalled-cycles-backend    #    3.62% backend  cycles idle

       0.019114911 seconds time elapsed

So, both versions ran 80M instructions, and dispatched 60M uops to execution ports. (or with a memory source dispatches to an ALU for the or, and a load port for the load, regardless of whether it was micro-fused or not in the rest of the pipeline. nop doesn't dispatch to an execution port at all.) Similarly, both versions retire 100M unfused-domain uops, because the 40M nops count here.

The difference is in the counters for the fused-domain.

1. The 1-register address version only issues and retires 80M fused-domain uops. This is the same as the number of instructions. Each insn turns into one fused-domain uop.


2. The 2-register address version issues 100M fused-domain uops. This is the same as the number of unfused-domain uops, indicating that no micro-fusion happened.

I suspect that you'd only see a difference between UOPS_ISSUED and UOPS_RETIRED(retirement slots used) if branch mispredicts led to uops being cancelled after issue, but before retirement.

And finally, the performance impact is real. The non-fused version took 1.5x as many clock cycles. This exaggerates the performance difference compared to most real cases. The loop has to run in a whole number of cycles, and the 2 extra uops push it from 2 to 3. Often, an extra 2 fused-domain uops will make less difference. And potentially no difference, if the code is bottlecked by something other than 4-fused-domain-uops-per-cycle.

Still, code that makes a lot of memory references in a loop might be faster if implemented with a moderate amount of unrolling and incrementing multiple pointers which are used with simple [base + immediate offset] addressing, instead of the using [base + index] addressing modes.

futher stuff

RIP-relative with an immediate can't micro-fuse. Agner Fog's testing shows that this is the case even in the decoders / uop-cache, so they never fuse in the first place (rather than being un-laminated).

IACA gets this wrong, and claims that both of these micro-fuse:

cmp dword  [abs mydata], 0x1b   ; fused counters != unfused counters (micro-fusion happened, and wasn't un-laminated).  Uses 2 entries in the uop-cache, according to Agner Fog's testing
cmp dword  [rel mydata], 0x1b   ; fused counters ~= unfused counters (micro-fusion didn't happen)

RIP-rel does micro-fuse (and stay fused) when there's no immediate, e.g.:

or  eax, dword  [rel mydata]    ; fused counters != unfused counters, i.e. micro-fusion happens

---

Micro-fusion doesn't increase the latency of an instruction. The load can issue before the other input is ready.

ALIGN 32
.dep_fuse:
    or eax, [rsi + 0]
    or eax, [rsi + 0]
    or eax, [rsi + 0]
    or eax, [rsi + 0]
    or eax, [rsi + 0]
    dec ecx
    jg .dep_fuse

This loop runs at 5 cycles per iteration, because of the eax dep chain. No faster than a sequence of or eax, [rsi + 0 + rdi], or mov ebx, [rsi + 0 + rdi] / or eax, ebx. (The unfused and the mov versions both run the same number of uops.) Scheduling / dep checking happens in the unfused-domain. Newly issued uops go into the scheduler (aka Reservation Station (RS)) as well as the ROB. They leave the scheduler after dispatching (aka being sent to an execution unit), but stay in the ROB until retirement. So the out-of-order window for hiding load latency is at least the scheduler size (54 unfused-domain uops in Sandybridge, 60 in Haswell, 97 in Skylake).

Micro-fusion doesn't have a shortcut for the base and offset being the same register. A loop with or eax, [mydata + rdi+4*rdi] (where rdi is zeroed) runs as many uops and cycles as the loop with or eax, [rsi+rdi]. This addressing mode could be used for iterating over an array of odd-sized structs starting at a fixed address. This is probably never used in most programs, so it's no surprise that Intel didn't spend transistors on allowing this special-case of 2-register modes to micro-fuse. (And Intel documents it as "indexed addressing modes" anyway, where a register and scale factor are needed.)

---

Macro-fusion of a cmp/jcc or dec/jcc creates a uop that stays as a single uop even in the unfused-domain. dec / nop / jge can still run in a single cycle but is three uops instead of one.

How to split one string into multiple variables in bash shell?

I've been looking for a solution and found similar questions, only they were attempting to split sentences with spaces between them, and the answers do not work for my situation.

Currently a variable is being set to something a string like this:
ABCDE-123456
and I would like to split that into 2 variables, while eliminating the "-". i.e.:
var1=ABCDE
var2=123456

How is it possible to accomplish this?

---

This is the solution that worked for me:
var1=$(echo $STR | cut -f1 -d-)
var2=$(echo $STR | cut -f2 -d-)

Is it possible to use the cut command that will work without a delimiter (each character gets set as a variable)?

var1=$(echo $STR | cut -f1 -d?)
var2=$(echo $STR | cut -f1 -d?)
var3=$(echo $STR | cut -f1 -d?)
etc.

Answer

If your solution doesn't have to be general, i.e. only needs to work for strings like your example, you could do:

var1=$(echo $STR | cut -f1 -d-)
var2=$(echo $STR | cut -f2 -d-)

I chose cut here because you could simply extend the code for a few more variables...

Unexpected Result With JavaScript Substr()

I'm having a problem with substr() in JavaScript.


Please look at the code below.

The following works as expected. y = 2017

var add_date = "20170505";
var y = add_date.substr(0, 4);
alert(y);

But... the following doesn't work. It should return '05' but instead it returns 0505. m = 0505

var add_date = "20170505";
var m = add_date.substr(4, 6);
alert(m);

Could someone explain me what's wrong?

Thanks,

Nathan

Answer

.substr(4,6) method returns 6 characters starting at index 4. Use .substring instead.

var add_date = "20170505",
    y = add_date.substring(0, 4);
    console.log(y);


var add_date = "20170505",
    m = add_date.substring(4, 6);
    console.log(m);

Strings in Java : equals vs ==

parsing - PHP Version 5.2.14 / Parse error: syntax error, unexpected T_FUNCTION, expecting ')'

I have a certain piece of code that I'm trying to use with PHP Version 5.2.14 . Is it incompatible?? I run the following,

jailshell-3.2$ php -l /XYZ/functions.php

And it gives:

Parse error: syntax error, unexpected T_FUNCTION, expecting ')' in /XYZ/functions.php on line 2115
Errors parsing /XYZ/functions.php

The code is:

2114    $range = array_map(
2115                function (DatePeriod $p) use ($vt2) {
2116               $res = array();